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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL(R) Dual-Port Static RAM
Features
* True dual-ported memory cells which allow simultaneous access of the same memory location * 4/8/16K x 16 and 8/16K x 8 organization * High-speed access: 35 ns * Ultra Low operating power -- Active: ICC = 15 mA (typical) at 55 ns -- Active: ICC = 25 mA (typical) at 35 ns -- Standby: ISB3 = 2 A (typical) * Small footprint: Available in a 6x6 mm 100-pin Lead(Pb)-free fBGA * Supports 1.8V, 2.5V, and 3.0V I/Os * Full asynchronous operation * Automatic power-down * Pin select for Master or Slave * Expandable data bus to 32 bits with Master/Slave chip select when using more than one device * On-chip arbitration logic * Semaphores included to permit software handshaking between ports * Input Read Registers and Output Drive Registers * INT flag for port-to-port communication * Separate upper-byte and lower-byte control * Industrial temperature ranges
Selection Guide for 1.8V
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 Typical Standby Current for ISB3 35 25 2 2 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 55 15 2 2
Unit ns mA A A
Selection Guide for 2.5V
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 Typical Standby Current for ISB3 35 39 6 4 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 55 28 6 4
Unit ns mA A A
Selection Guide for 3.0V
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 Typical Standby Current for ISB3 35 49 7 6 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 55 42 7 6
Unit ns mA A A
Cypress Semiconductor Corporation Document #: 38-06081 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised October 31, 2005
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
I/O[15:0]L UBL LBL IO Control IO Control
I/O[15:0]R UBR LBR
16K X 16 Dual Ported Array
Address Decode
Address Decode
A[13:0]L CE L OE L R/W L SEML BUSY L INTL Mailboxes
Interrupt Arbitration Semaphore
A [13:0]R CE R OE R R/W R SEMR BUSY R
INTR
M/S
IRR0 ,IRR1
CEL OEL R/WL
Input Read Register and Output Drive Register
CE R OE R R/W R ODR0 - ODR4
SFEN
Figure 1. Top Level Block Diagram[1,2]
Notes: 1. A0-A11 for 4K devices; A0-A12 for 8K devices; A0-A13 for 16K devices. 2. BUSY is an output in master mode and an input in slave mode.
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Pin Configurations [3, 4, 5, 6, 7, 8]
100-Ball 0.5-mm Pitch BGA Top View CYDM064A16/CYDM128A16/CYDM256A16
1 A B C A5R A3R A0R 2 A8R A4R A1R 3 A11R A7R A2R 4 UBR A9R A6R INTR INTL A1L A12L[3] LBL IRR0[5] UBL 4 5 VSS CER LBR A10R VSS VCC OEL CEL VCC SEML 5 6 SEMR R/WR 7 I/O15R OER 8 I/O12R VCC I/O11R I/O8R VCC I/O0R I/O12L NC [7] I/O6L I/O2L 8 9 I/O10R I/O9R I/O7R I/O5R I/O1R I/O15L I/O14L NC[7] I/O8L I/O5L 9 10 VSS I/O6R VSS I/O2R VSS VCC A B C D E F
IRR1[6] I/O14R A12R[3] VSS VSS I/O3L I/O1L VSS R/WL 6 I/O13R I/O4R I/O3R I/O11L VCC I/O4L I/O0L 7
D ODR4 ODR2 BUSYR E VSS M/S ODR3
F SFEN [8] ODR1 BUSYL G ODR0 H J K A0L A3L A6L 1 A2L A4L A7L A8L 2 A5L A9L A10L A11L 3
I/O13L G I/O10L H I/O9L I/O7L 10 J K
Notes: 3. A12L and A12R are NC pins for CYDM064A16. 4. IRR functionality is not supported for the CYDM256A16 device. 5. This pin is A13L for CYDM256A16 device. 6. This pin is A13R for CYDM256A16 device. 7. Leave this pin unconnected. No trace or power component can be connected to this pin. 8. IRR functionality not supported for the CYDM256A16 device. Connect this pin to VCC.
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Pin Configurations (continued)[7, 9, 10, 11,12, 13]
100-Ball 0.5-mm Pitch BGA Top View CYDM064A08/CYDM128A08
1 A B C A5R A3R A0R 2 A8R A4R A1R 3 A11R A7R A2R 4 VCC A9R A6R INTR INTL A1L A12L VSS IRR0
[10]
5 VSS CER VSS A10R VSS VCC OEL CEL VCC SEML 5
6 SEMR R/WR IRR1[11] A12R VSS VSS I/O3L I/O1L VSS R/WL 6
7 VSS OER VSS VSS I/O4R I/O3R VSS VCC I/O4L I/O0L 7
8 VSS VCC VSS VSS VCC I/O0R VSS NC[12] I/O6L I/O2L 8
9 VSS VSS I/O7R I/O5R I/O1R VSS VSS NC[12] VSS I/O5L 9
10 VSS I/O6R VSS I/O2R VSS VCC VSS VSS VSS I/O7L 10 A B C D E F G H J K
D ODR4 ODR2 BUSYR E VSS M/ S ODR3
F SFEN[13] ODR1 BUSYL G ODR0 H J K A0L A3L A6L 1 A2L A4L A7L A8L 2 A5L A9L A10L A11L 3
VCC 4
Notes: 9. IRR functionality is not supported for the CYDM128A08 device. 10. This pin is A13L for CYDM128A08 devices. 11. This pin is A13R for CYDM128A08 devices. 12. Leave this pin unconnected. No trace or power component can be connected to this pin. 13. IRR functionality is not supported for the CYDM128A08. Connect this pin to VDD.
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Pin Definitions
Left Port CEL R/WL OEL A0L-A13L I/O0L-I/O15L SEML UBL LBL INTL BUSYL Right Port CER R/WR OER A0R-A13R I/O0R-I/O15R SEMR UBR LBR INTR BUSYR IRR0, IRR1 ODR0-ODR4 SFEN M/S VCC GND NC Chip Enable Read/Write Enable Output Enable Address (A0-A11 for 4K devices; A0-A12 for 8K devices; A0-A13 for 16K devices). Data Bus Input/Output for x16 devices; I/O0-I/O7 for x8 devices. Semaphore Enable Upper Byte Select (I/O8-I/O15 for x16 devices; Not applicable for x8 devices). Lower Byte Select (I/O0-I/O7 for x16 devices; Not applicable for x8 devices). Interrupt Flag Busy Flag Input Read Register for CYDM064A16, CYDM064A08, CYDM128A16. A13L, A13R for CYDM256A16 and CYDM128A08 devices. Output Drive Register; These outputs are Open Drain. Special Function Enable Master or Slave Select Power Ground No Connect. Leave this pin Unconnected. The CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 are available in 100-ball 0.5-mm Pitch Ball Grid Array (BGA) packages. Power Supply The core and I/O voltages will be 1.8V/2.5V LVCMOS/3.0V LVTTL depending on the user's supply voltage. The supply voltage controls both the Core and I/O voltages. Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFF for the CYDM064A16, 1FFF for the CYDM128A16 and CYDM064A08, Page 5 of 25 Description
Functional Description
The CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 are low-power CMOS 4K, 8K,16K x 16, and 8/16K x 8 dual-port static RAMs. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a Chip Enable (CE) pin.
Document #: 38-06081 Rev. *F
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
3FFF for the CYDM256A16 and CYDM128A08) is the mailbox for the right port and the second-highest memory location (FFE for the CYDM064A16, 1FFE for the CYDM128A16 and CYDM064A08, 3FFE for the CYDM256A16 and CYDM128A08) is the mailbox for the left port. When one port writes to the other port's mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user-defined. Each port can read the other port's mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor's interrupt request input pin. On power up, an initialization program should be run and the interrupts for both ports must be read to reset them. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports' CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Input Read Register The Input Read Register (IRR) captures the status of two external input devices that are connected to the Input Read pins. The contents of the IRR read from address x0000 from either port. During reads from the IRR, DQ0 and DQ1 are valid bits and DQ<15:2> are don't care. Writes to address x0000 are not allowed from either port. Address x0000 is not available for standard memory accesses when SFEN = VIL. When SFEN = VIH, address x0000 is available for memory accesses. The inputs will be 1.8V/2.5V LVCMOS/3.0V LVTTL depending on the user's supply voltage. Refer to Table 3 for Input Read Register operation. Output Drive Register The Output Drive Register (ODR) determines the state of up to five external binary state devices by providing a path to VSS for the external circuit. These outputs are Open Drain. The five external devices can operate at different voltages (1.5V VDDIO 3.5V) but the combined current cannot exceed 40 mA (8 mA max for each external device). The status of the ODR bits are set using standard write accesses from either port to address x0001 with a "1" corresponding to on and "0" corresponding to off. The status of the ODR bits can be read with a standard read access to address x0001. When SFEN = VIL, the ODR is active and address x0001 is not available for memory accesses. When SFEN = VIH, the ODR is inactive and address x0001 can be used for standard accesses. During reads and writes to ODR DQ<4:0> are valid and DQ<15:5> are don't care. Refer to Table 4 for Output Drive Register operation. Semaphore Operation The CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0-2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 5 shows sample semaphore operations. When reading a semaphore, all sixteen/eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no Page 6 of 25
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
guarantee which side will control the semaphore. On power-up, both ports should write "1" to all eight semaphores. access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device.
Architecture
The CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 consist of an array of 4K, 8K, or 16K words of 16 dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). The CYDM064A08 and CYDM128A08 consist of an array of 8K and 16K words of 8 each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W).These control pins permit independent Table 1. Non-Contending Read/Write Inputs CE H X L L L L L L X H X H X L L X X R/W X X L L L H H H X H H OE X X X X X L L L H L L X X X X UB X H L H L L H L X X H X H L X LB X H H L L H L L X X H X H X L SEM H H H H H H H H X L L L L L L High Z High Z Data In High Z Data In
Outputs I/O8-I/O15[14] I/O0-I/O7 High Z High Z High Z Data In Data In High Z Data Out Data Out High Z Data Out Data Out Data In Data In Operation Deselected: Power-down Deselected: Power-down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Read Data in Semaphore Flag Read Data in Semaphore Flag Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag Not Allowed Not Allowed
Data Out High Z Data Out High Z Data Out Data Out Data In Data In
Table 2. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH)[15] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X X CEL L X X L OEL X X X L A0L-13L 3FFF X X 3FFE[18]
[18]
Right Port INTL X X L[16] H[17] R/WR X X L X CER X L L X OER X L X X A0R-13R X 3FFF[18] 3FFE[18] X INTR L[17] H[16] X X
Table 3. Input Read Register Operation[19, 22] SFEN H L CE L L R/W H H OE L L UB L X LB L L ADDR x0000 I/O0-I/O1 I/O2-I/O15
[20]
Mode Standard Memory Access IRR Read
x0000-Max VALID
VALID[20] X
VALID[21]
Notes: 14. This column applies to x16 devices only. 15. See Interrupts Functional Description for specific highest memory locations by device. 16. If BUSYR = L, then no change. 17. If BUSYL = L, then no change. 18. See Functional Description for specific addresses by device. 19. SFEN = VIL for IRR reads 20. UB or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid. 21. LB must be active (LB = VIL) for these bits to be valid. 22. SFEN active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH.
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Table 4. Output Drive Register [25] SFEN H L L CE L L L R/W H L H OE X
[26]
UB L
[23]
LB L
[23]
I/O0-I/O4 I/O5-I/O15 Mode [23] [23] x0000-Max VALID VALID Standard Memory Access x0001 x0001 VALID[24] VALID[24] X X ODR Write[25, 27] ODR Read[25]
ADDR
X L
X X
L L
Table 5. Semaphore Operation Example Function No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O0-I/O15 Left I/O0-I/O15 Right 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 Semaphore-free Left Port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore-free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore-free Status
Notes: 23. UB or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid. 24. LB must be active (LB = VIL) for these bits to be valid. 25. SFEN = VIL for ODR reads and writes. 26. Output enable must be low (OE = VIL) during reads for valid data to be output. 27. During ODR writes data will also be written to the memory
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Maximum Ratings[28]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +3.3V DC Voltage Applied to Outputs in High-Z State..........................-0.5V to VCC + 0.5V DC Input Voltage[29] ...............................-0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 90 mA Static Discharge Voltage.......................................... > 2000V Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 1.8V 100 mV 2.5V 100 mV 3.0V 300 mV 1.8V 100 mV 2.5V 100 mV 3.0V 300 mV
Industrial
-40C to +85C
Electrical Characteristics for 1.8V Over the Operating Range
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Parameter VOH VOL VOL ODR VIH VIL IOZ ICEXODR IIX ICC ISB1 Description Output HIGH Voltage (IOH = -100 A) Output LOW Voltage (IOL = 100 A) ODR Output LOW Voltage (IOL = 2 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current ODR Output Leakage Current. VOUT = VCC Input Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Ind. Outputs Disabled Standby Current (Both Ports TTL Level) CEL Ind. and CER VCC - 0.2, SEML = SEMR = SFEN = VCC - 0.2, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Ind. 1.2 -0.2 -1 -1 -1 25 2 Min. VCC - 0.2 0.2 0.2 VCC + 0.2 0.4 1 1 1 40 6 1.2 -0.2 -1 -1 -1 15 2 Typ. Max. Min. VCC - 0.2 0.2 0.2 VCC + 0.2 0.4 1 1 1 25 6 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 Typ. Max. Unit V V V V V A A A mA A
ISB2 ISB3
8.5 2
18 6
8.5 2
14 6
mA A
Standby Current (Both Ports CMOS Level) CEL Ind. & CER VCC - 0.2V, SEML, SEMR, and SFEN> VCC - 0.2V, f = 0 Standby Current (One Port CMOS Level) CEL Ind. | CER VIH, f = fMAX[30]
ISB4
8.5
18
8.5
14
mA
Notes: 28. The voltage on any input or I/O pin can not exceed the power pin during power-up. 29. Pulse width < 20 ns. 30. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Electrical Characteristics for 2.5V Over the Operating Range
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Parameter VOH VOL VOL ODR VIH VIL IOZ ICEXODR IIX ICC ISB1 Description Output HIGH Voltage (IOH = -2 mA) Output LOW Voltage (IOL = 2 mA) ODR Output LOW Voltage (IOL = 5 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current ODR Output Leakage Current. VOUT = VCC Input Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Ind. 1.7 -0.3 -1 -1 -1 39 6 Min. 2.0 0.4 0.4 VCC + 0.3 0.6 1 1 1 55 8 1.7 -0.3 -1 -1 -1 28 6 Typ. Max. Min. 2.0 0.4 0.4 VCC + 0.3 0.6 1 1 1 40 8 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 Typ. Max. Unit V V V V V A A A mA A
Standby Current (Both Ports TTL Ind. Level) CEL and CER VCC - 0.2, SEM L= SEMR = SFEN = VCC - 0.2, f=fMAX Standby Current (One Port TTL Ind. Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL & CER VCC - 0.2V, SEML, SEMR, and SFEN> VCC - 0.2V, f = 0 Ind.
ISB2 ISB3
21 4
30 6
18 4
25 6
mA A
ISB4
Standby Current (One Port CMOS Ind. Level) CEL | CER VIH, f = fMAX[30]
21
30
18
25
mA
Electrical Characteristics for 3.0V Over the Operating Range
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Parameter VOH VOL VOL ODR VIH VIL IOZ ICEXODR IIX Description Output HIGH Voltage (IOH = -2 mA) Output LOW Voltage (IOL = 2 mA) ODR Output LOW Voltage (IOL = 8 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current ODR Output Leakage Current. VOUT = VCC Input Leakage Current 2.0 -0.2 -1 -1 -1 Min. 2.1 0.4 0.5 VCC + 0.2 0.7 1 1 1 2.0 -0.2 -1 -1 -1 Typ. Max. Min. 2.1 0.4 0.5 VCC + 0.2 0.7 1 1 1 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 Typ. Max. Unit V V V V V A A A
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Electrical Characteristics for 3.0V Over the Operating Range (continued)
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Parameter ICC ISB1 Description Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Ind. Min. Typ. 49 7 Max. 70 10 Min. CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 Typ. 42 7 Max. 60 10 Unit mA A
Standby Current (Both Ports TTL Ind. Level) CEL and CER VCC - 0.2, SEML = SEMR = SFEN = VCC - 0.2, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL & CER VCC - 0.2V, SEML, SEMR, and SFEN> VCC - 0.2V, f = 0 Ind. Ind.
ISB2 ISB3
28 6
40 8
25 6
35 8
mA A
ISB4
Standby Current (One Port CMOS Ind. Level) CEL | CER VIH, f = fMAX[30]
28
40
25
35
mA
Capacitance[31]
Parameter CIN COUT
7
Description Input Capacitance Output Capacitance
Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V
Max. 9 10
Unit pF pF
AC Test Loads and Waveforms
3.0V/2.5V/1.8V 3.0V/2.5V/1.8V R1 OUTPUT C = 30 pF R2 OUTPUT C = 30 pF VTH = 0.8V RTH = 6 k R1 OUTPUT C = 5 pF R2
(a) Normal Load (Load 1) 3.0V/2.5V R1 R2 1022 792 1.8V 13500 10800
1.8V GND
(b) Thevenin Equivalent (Load 1) ALL INPUT PULSES
90% 90% 10% 3 ns
(c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, and tLZWE including scope and jig)
10% 3 ns
Note: 31. Tested initially and after any design or process changes that may affect these parameters.
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Characteristics for 1.8V Over the Operating Range[32]
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Parameter Read Cycle tRC tAA tOHA tACE[33] tDOE tLZOE
[34, 35, 36]
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 Min. 55 Max. Unit ns 55 5 55 30 5 25 5 25 0 55 55 55 45 45 0 0 40 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 0 80 65 45 45 45 45 ns ns ns ns ns ns ns ns
Description Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down Byte Enable Access Time Write Cycle Time CE LOW to Write End Address Valid to Write End Address Hold From Write End Address Set-up to Write Start Write Pulse Width Data Set-up to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid
Min. 35
Max.
35 5 35 20 5 15 5 15 0 35 35 35 25 25 0 0 25 20 0 15 0 50 40 25 25 25 25
tHZOE[34, 35, 36] tLZCE[34, 35, 36] tHZCE[34, 35, 36] tPU[36] tPD[36] tABE[33] Write Cycle tWC tSCE[33] tAW tHA tSA[33] tPWE tSD tHD tHZWE[35, 36] tLZWE[35, 36] tWDD[37] tDDD[37] Busy Timing tBLA tBHA tBLC tBHC
[38]
BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH
Notes: 32. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VDD/2, input pulse levels of 0 to VDD, and output loading of the specified IOI/IOH and 30-pF load capacitance. 33. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 34. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 35. Test conditions used are Load 3. 36. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 37. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 38. Test conditions used are Load 2.
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Characteristics for 1.8V Over the Operating Range[32] (continued)
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Parameter tPS tWB tWH tBDD[39] tINS tINR tSOP tSWRD tSPS tSAA Description Port Set-up for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time 10 10 10 35 Min. 5 0 20 25 31 31 15 10 10 55 Max. Min. 5 0 35 40 45 45 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 Max. Unit ns ns ns ns ns ns ns ns ns ns
Interrupt Timing[38]
Semaphore Timing
Switching Characteristics for 2.5V Over the Operating Range
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Parameter Read Cycle tRC tAA tOHA tACE[33] tDOE tLZOE[34, 35, 36] tHZOE[34, 35, 36] tLZCE[34, 35, 36] tHZCE[34, 35, 36] tPU[36] tPD[36] tABE[33] Write Cycle tWC tSCE[33] Write Cycle Time CE LOW to Write End 35 25 55 45 ns ns Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down Byte Enable Access Time 0 35 35 2 15 0 55 55 2 15 2 25 5 35 20 2 25 35 35 5 55 30 55 55 ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 Max. Unit
Notes: 39. tBDD is a calculated parameter and is the greater of tWDD-tPWE (actual) or tDDD-tSD (actual).
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Characteristics for 2.5V Over the Operating Range (continued)
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Parameter tAW tHA tSA[33] tPWE tSD tHD tHZWE[35, 36] tLZWE[35, 36] tWDD[37] tDDD[37] Busy Timing tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[39] Interrupt Timing tINS tINR tSOP tSWRD tSPS tSAA
[38]
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 Min. 45 0 0 40 30 0 Max. Unit ns ns ns ns ns ns 25 0 80 65 45 45 45 45 5 0 35 ns ns ns ns ns ns ns ns ns ns ns 40 45 45 15 10 10 ns ns ns ns ns ns 55 ns
Description Address Valid to Write End Address Hold From Write End Address Set-up to Write Start Write Pulse Width Data Set-up to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set-up for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid
[38]
Min. 25 0 0 25 20 0
Max.
15 0 50 40 25 25 25 25 5 0 20 25 31 31 10 10 10 35
INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time
Semaphore Timing
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Characteristics for 3.0V Over the Operating Range
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Parameter Read Cycle tRC tAA tOHA tACE[33] tDOE tLZOE
[34, 35, 36]
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 Min. 55 Max. Unit ns 55 5 55 30 1 25 1 25 0 55 55 55 45 45 0 0 40 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 0 80 65 45 45 45 45 5 0 35 ns ns ns ns ns ns ns ns ns ns ns 40 ns
Description Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down Byte Enable Access Time Write Cycle Time CE LOW to Write End Address Valid to Write End Address Hold From Write End Address Set-up to Write Start Write Pulse Width Data Set-up to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid
Min. 35
Max.
35 5 35 20 1 15 1 15 0 35 35 35 25 25 0 0 25 20 0 15 0 50 40 25 25 25 25 5 0 20 25
tHZOE[34, 35, 36] tLZCE[34, 35, 36] tHZCE[34, 35, 36] tPU[36] tPD[36] tABE[33] Write Cycle tWC tSCE[33] tAW tHA tSA[33] tPWE tSD tHD tHZWE[35, 36] tLZWE[35, 36] tWDD[37] tDDD[37] Busy Timing tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[39]
[38]
BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set-up for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Characteristics for 3.0V Over the Operating Range (continued)
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Parameter Interrupt Timing[38] tINS tINR tSOP tSWRD tSPS tSAA INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time 10 10 10 35 31 31 15 10 10 55 45 45 ns ns ns ns ns ns Description Min. Max. Min. CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 Max. Unit
Semaphore Timing
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[40, 41, 42]
tRC ADDRESS tOHA DATA OUT tAA DATA VALID tOHA
PREVIOUS DATA VALID
Read Cycle No.2 (Either Port CE/OE Access)[40, 43, 44]
tACE tDOE tLZOE DATA OUT tLZCE tPU ICC CURRENT ISB tPD DATA VALID tHZCE tHZOE
CE and LB or UB OE
Notes: 40. R/W is HIGH for read cycles. 41. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 42. OE = VIL. 43. Address valid prior to or coincident with CE transition LOW. 44. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Waveforms (continued)
Read Cycle No. 3 (Either Port)[40, 42, 45, 46]
tRC ADDRESS tAA UB or LB tHZCE tLZCE tABE CE tACE tLZCE DATA OUT tHZCE tOHA
Write Cycle No.1: R/W Controlled Timing[45, 46, 47, 48, 49, 50]
tWC ADDRESS tHZOE [51] OE tAW CE
[49, 50]
tSA R/W tHZWE[51] DATA OUT NOTE 52
tPWE[48]
tHA
tLZWE NOTE 52 tSD tHD
DATA IN
Notes: 45. R/W must be HIGH during all address transitions. 46. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 47. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 48. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 49. To access RAM, CE = VIL, SEM = VIH. 50. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 51. Transition is measured 0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 52. During this period, the I/O pins are in the output state, and input signals must not be applied.
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Waveforms (continued)
Write Cycle No. 2: CE Controlled Timing[45, 46, 47, 52]
tWC ADDRESS tAW CE
[49, 50]
tSA R/W
tSCE
tHA
tSD DATA IN
tHD
Semaphore Read After Write Timing, Either Side[53, 54]
tSAA A0-A2 VALID ADRESS tAW SEM tSCE tSD I/O0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE tDOE DATAIN VALID tPWE tHD DATAOUT VALID tHA tSOP VALID ADRESS tACE tOHA
Notes: 53. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 54. CE = HIGH for the duration of the above timing (both write and read cycle).
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Waveforms (continued)
Timing Diagram of Semaphore Contention[55, 56]
A0L-A2L
MATCH
R/WL SEML tSPS A0R-A2R MATCH
R/WR SEMR
Timing Diagram of Read with BUSY (M/S= HIGH)[57]
tWC ADDRESSR R/WR MATCH tPWE tSD DATA INR tPS ADDRESSL MATCH tBLA BUSYL tDDD DATAOUTL tWDD
Notes: 55. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 56. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. 57. CEL = CER = LOW.
tHD
VALID
tBHA tBDD
VALID
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Waveforms (continued)
Write Timing with Busy Input (M/S = LOW)
tPWE
R/W tWB
BUSY
tWH
Busy Timing Diagram No.1 (CE Arbitration) CEL Valid First[58]
ADDRESSL,R CEL tPS ADDRESS MATCH
CER
tBLC BUSYR
tBHC
CER Valid First
ADDRESSL,R CER tPS ADDRESS MATCH
CEL
tBLC BUSYL
tBHC
Note: 58. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Waveforms (continued)
Busy Timing Diagram No.2 (Address Arbitration)[58] Left Address Valid First
tRC or tWC ADDRESSL ADDRESS MATCH tPS ADDRESSR tBLA BUSYR tBHA ADDRESS MISMATCH
Right Address Valid First
tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSYL tBHA ADDRESS MISMATCH
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Switching Waveforms (continued)
Interrupt Timing Diagrams Left Side Sets INTR:
ADDRESSL CEL R/WL INTR tINS [60] tWC WRITE 1FFF (OR 1/3FFF) tHA[59]
Right Side Clears INTR:
ADDRESSR CER tINR [60] R/WR OER INTR
tRC READ 7FFF (OR 1/3FFF)
Right Side Sets INTL:
ADDRESSR CER R/WR INTL tINS
[60]
tWC WRITE 1FFE (OR 1/3FFE) tHA[59]
Left Side Clears INTL:
ADDRESSR CEL tINR[60] R/WL OEL INTL
Notes: 59. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 60. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
tRC READ 7FFE OR 1/3FFE)
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Ordering Information
16K x16 1.8V Asynchronous Dual-Port SRAM Speed (ns) 35 55 55 Speed (ns) 35 55 55 Speed (ns) 35 55 55 Speed (ns) 35 55 55 Speed (ns) 35 55 55 Ordering Code CYDM256A16-35BVXC CYDM256A16-55BVXC CYDM256A16-55BVXI Package Name BZ100 BZ100 BZ100 Package Name BZ100 BZ100 BZ100 Package Name BZ100 BZ100 BZ100 Package Name BZ100 BZ100 BZ100 Package Name BZ100 BZ100 BZ100 Package Type 100-Ball Lead Free 0.5-mm Pitch BGA 100-Ball Lead Free 0.5-mm Pitch BGA 100-Ball Lead Free 0.5-mm Pitch BGA Operating Range Commercial Commercial Industrial Operating Range Commercial Commercial Industrial Operating Range Commercial Commercial Industrial Operating Range Commercial Commercial Industrial Operating Range Commercial Commercial Industrial
8K x16 1.8V Asynchronous Dual-Port SRAM Ordering Code CYDM128A16-35BVXC CYDM128A16-55BVXC CYDM128A16-55BVXI Package Type 100-Ball Lead Free 0.5-mm Pitch BGA 100-Ball Lead Free 0.5-mm Pitch BGA 100-Ball Lead Free 0.5-mm Pitch BGA
4K x16 1.8V Asynchronous Dual-Port SRAM Ordering Code CYDM064A16-35BVXC CYDM064A16-55BVXC CYDM064A16-55BVXI Package Type 100-Ball Lead Free 0.5-mm Pitch BGA 100-Ball Lead Free 0.5-mm Pitch BGA 100-Ball Lead Free 0.5-mm Pitch BGA
16K x8 1.8V Asynchronous Dual-Port SRAM Ordering Code CYDM128A08-35BVXC CYDM128A08-55BVXC CYDM128A08-55BVXI Package Type 100-Ball Lead Free 0.5-mm Pitch BGA 100-Ball Lead Free 0.5-mm Pitch BGA 100-Ball Lead Free 0.5-mm Pitch BGA
8K x8 1.8V Asynchronous Dual-Port SRAM Ordering Code CYDM064A08-35BVXC CYDM064A08-55BVXC CYDM064A08-55BVXI Package Type 100-Ball Lead Free 0.5-mm Pitch BGA 100-Ball Lead Free 0.5-mm Pitch BGA 100-Ball Lead Free 0.5-mm Pitch BGA
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CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Package Diagram
100 VFBGA (6 x 6 x 1.0 mm) BZ100A
51-85209-*B
MoBL is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08
Document History Page
Document Title: CYDM064A16/CYDM128A16/CYDM256A16/CYDM064A08/CYDM128A08 1.8V 4K/8K/16K x 16 and 8K/16K x 8 Dual-Port Static RAM Document Number: 38-06081 REV. ** *A ECN NO. 272872 300481 Issue Date SEE ECN SEE ECN Orig. of Change SPN SPN New data sheet Updated x8 pinout, added lead free information, updated part numbers, updated max. supply voltage to ground potential, added package drawing, added open drain output information for ODR, Updated tBDD, updated package name Updated tINS, tHZOE, tHZCE Updated note 32 Added electrical characteristics for 2.5V and 3.0V Added timing values for 2.5V and 3.0V Updated ISB1 and ISB3 definition Added ICEX for all voltages Added VOL ODR for all voltages Removed Preliminary Updated tINS and tINR to 28ns Updated 2.5V/3.0V ICC, ISB1, ISB2, ISB4 Changed 2.5V VIL to 0.6V and 3.0V VIL to 0.7V (typo) Updated ISB2 and ISB4 typo to mA. Updated tINS and tINR for -55 to 31ns. Updated IOH and IOL values for the 2.5V and 3.0V parameters VOH and VOL Description of Change
*B *C
333516 363174
SEE ECN SEE ECN
SPN SPN
*D
381701
SEE ECN
YDT
*E *F
396697 404588
SEE ECN SEE ECN
KGH KGH
Document #: 38-06081 Rev. *F
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